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Theoretical design of quantum-tunneling-enabled ultra-steep-slope bipolar reconfigurable logic field-effect transistors based on 2D Janus XMoSiN(2) (X = O, S, Se, Te) monolayers

AI Summary
  • Janus SMoSiN2 monolayer exhibits near-perfect electron-hole effective mass symmetry and a 2.16 eV direct bandgap enabling bipolar reconfigurable FET channels.
  • Split-gate lateral heterostructure and doping-engineered tunnelling FET architectures enable in situ voltage-switchable polarity via quantum tunnelling injection, bypassing the thermionic limit.
  • Quantum-tunnelling devices achieve 28 mV decade subthreshold swing and enable XNOR, half-adders and decoders, reducing transistor count by up to 88.9%.
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Phys Chem Chem Phys. 2026 Sep 18. doi: 10.1039/d6cp02621d. Online ahead of print.

ABSTRACT

Two-dimensional (2D) semiconductors have long been proposed as channel materials for post-complementary metal-oxide-semiconductor (CMOS) electronics. However, their practical impact remains constrained by asymmetric electron-hole transport and the absence of dynamic polarity control. This study presents a theoretical investigation combining first-principles electronic structure calculations with quantum tunneling transport simulations, proposing a 2D Janus SMoSiN2 monolayer material that exhibits nearly perfect electron-hole effective mass symmetry and a direct bandgap of 2.16 eV, making it suitable for constructing a novel class of bipolar reconfigurable field-effect transistors. By engineering two device architectures: a split-gate lateral heterostructure FET and a doping-engineered tunnelling FET, we demonstrate in situ, voltage-switchable polarity between n-type and p-type operation. Both designs operate through a quantum-tunnelling injection mechanism that bypasses the thermionic limit, yielding a minimum subthreshold swing of 28 mV per decade at room temperature, well below the 60 mV per decade Boltzmann bound. Using these devices as building blocks, we construct single-transistor XNOR gates and multi-transistor logic units that assemble into functional circuits such as half-adders and decoders. This architecture achieves an up to 88.9% reduction in transistor count compared with conventional CMOS implementations. Our findings establish 2D Janus monolayers as a platform for ultra-low-power, high-density reconfigurable integrated circuits.

PMID:42757584 | DOI:10.1039/d6cp02621d

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